JOB: DESIGN ENGINEER II IN CADENCE IN BENGALURU Full Time

Location: Bengaluru

Company: Cadence

The role will be a key player in the organisation, responsible for characterising and validating Analogue and Digital IP-based Silicon Solutions at Cadence.

Candidate should possess strong leadership skills with the ability to manage multiple priorities and guide team members on day-to-day lab tests and silicon characterisation activities. Ownership of tasks, ability to collaborate with remote teams located worldwide and clear communication skills are must-have attributes in this role. Coordination with R&D, Marketing teams in defining the scope and delivering the results in time are critical.

Experience: 2-5 yrs or Equivalent or relevant

Minimum Qualifications & Professional Experience

• 2-5 years (with BTech) or 4 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing.
• 2-3 years of management experience leading/mentoring a small team of engineers
• Physical Layer and Protocol layer experience on AT LEAST ONE High speed SERDES on Ethernet/PCIe/CXL/UCIe/
• Debug skills and Experience in using lab equipment such as Oscilloscopes, Bit Error Rate Testers, Protocol Exercisers, Analyzers.
• Proficient with Ethernet, PCIe, UCIe standards and Protocols. Proven experience in interpreting the standard’s specification to develop Electrical and Protocol, Interoperability and Compliance test suites to validate the silicon.
• Ability to isolate the PHY and controller (MAC/PCS) features to test, develop calibration/compliance lab suites and characterise.
• Architect and design Printed circuit boards in Schematic and layout level. Familiarity with peripheral chips, high-speed interface design techniques, Signal and Power integrity checks/analysis and fixes needed to meet the performance requirements.
• Experience in PCIe/UCIe LTSSM states / UCIe Interfaces / Ethernet standards is a plus.
• Proven experience in developing lab automation scripts and test result analysis to debug and root cause silicon failures.
• Expertise in developing ESD/Latchup/ HTOL tests to meet industry standards, reliability qualification & specification
• Expert level knowledge in Verilog RTL coding for FPGA, python, C/C++