ASIC Verification Engineer Full Time

Job Title: ASIC Verification Engineer

Location: Hyderabad

Job type : Contract

Experience: 5- 10 Years

We are hiring for one of the top IT services companies.

SPADTEK Solutions is proud to collaborate with leading IT organizations to source exceptional talent for their full-time positions. Client/Implementation Partner is a globally recognized IT services and consulting company, trusted by Fortune 500 clients and enterprises worldwide. With a strong presence across cloud, data engineering, AI, and digital transformation and is known for delivering cutting-edge solutions that drive business growth and innovation.

Working on enterprise-scale projects with global clients.

Exposure to next-gen technologies across cloud, data, and digital platforms.

A culture that values continuous learning, collaboration, and career growth.

Being part of a company consistently ranked among the top IT employers.

If you are an experienced professional seeking a long-term career opportunity with one of the industry s most respected names, this is your chance to join top IT services company through SPADTEK Solutions.

Job Summary

We are seeking an experienced ASIC Verification Engineer with strong expertise in IP, Block, Subsystem, and SoC verification. The ideal candidate should have hands-on experience in developing UVM-based verification environments, protocol verification, and creating comprehensive test plans for complex ASIC designs.

Key Responsibilities

5 – 10 years of relevant ASIC Verification experience.

Strong expertise in UVM and SystemVerilog.

Experience working on complex IPs, subsystems, and SoC verification projects.

Develop and execute verification plans for IP, Block, Subsystem, and SoC-level designs.

Design and implement UVM-based SystemVerilog testbenches.

Create and maintain verification environments, test cases, checkers, assertions, and coverage models.

Verify high-speed interfacs and protocols including DDR, PCIe, ONFI, and NVMe.

Define and review block-level, subsystem-level, and SoC-level verification test plans.

Analyze simulation results, debug failures, and drive issue resolution.

Monitor and improve verification quality metrics and coverage closure.

Minimum 5 years of experience in IP/Block/Subsystem Verification (RTL Front-End Verification).

Strong expertise in SystemVerilog (SV) and UVM Verification with at least 4 years of hands-on experience.

Experience with standard bus interfaces such as AXI and AHB

Hands-on experience in verifying protocols such as DDR, PCIe, ONFI, or NVMe

Strong knowledge of ASIC simulation tools and advanced verification methodologies.

Experience in writing and executing block-level and SoC-level test plans.

Excellent debugging and problem-solving skills.

Experience with NAND, DDR, and PCIe IP/Subsystem verification.

Knowledge of scripting languages such as Python or Perl.

Exposure to coverage-driven verification methodologies.

Experience working in complex SoC environments.